A3S64D40GTP A3S56D40GTP A3S28D40JTP 力积电子 DDR1 SDRAM -【深圳市佳源伟业电子有限公司】电子元器件代理商和电子产品厂商

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ZILLTEK

ZILLTEK钰太科技成立于2005年12月12日台湾新竹，是一家专业模拟及混合讯号IC设计公司。成立至今积极投注研发资源、快速开发新产品。

钰太科技的产品线包含了从触控屏幕控制IC，电源管理IC（A. DC / DC转换; B. AC / DC转换），白光LED驱动器及MEMS Microphone sensor等，主要用于消费产品的应用，如无线宽带，数据通信（AP路由器，IAD，GPON等USB 3.0应用程序（Pen Driver，SSD，硬盘等），液晶电视 /显示器，机顶盒，监视（CCTV，IP CAM，婴儿监视器等），平板计算机，MID，PDA，DVD播放器，IA, Smart phone, NoteBook产品等。

A3S64D40GTP A3S56D40GTP A3S28D40JTP ZENTEL DDR1 SDRAM

A3S28D40JTP is a 4-bank x 2,097,152-word
x 16bit double data rate synchronous DRAM ,
with SSTL_2 interface. All control and address signals
are referenced to the rising edge of CLK.
Input data is registered on both edges of data strobe ,
and output data and data strobe are referenced on both edges of CLK.
The A3S28D40JTP achieves very high speed clock rate up to 200 MHz .

A3S64D40GTP A3S56D40GTP ZENTEL DDR1 SDRAM

FEATURES

-VDD=VDDQ=2.5V+0.2V

- Operating Temperature:

Commercial: 0 ~ 70℃

Industrial : -40 ~ 85℃

- Double data rate architecture ; two data transfers per clock cycle.

- Bidirectional , data strobe (DQS) is transmitted/received with data

- Differential clock input (CLK and /CLK)

- DLL aligns DQ and DQS transitions with CLK transitions edges of DQS

- Commands entered on each positive CLK edge ;

- Data and data mask referenced to both edges of DQS

- 4 bank operation controlled by BA0 , BA1 (Bank Address)

- CAS latency 2 / 2.5 / 3 (programmable) ;

- Burst length 2 / 4 / 8 (programmable)

- Burst type: Sequential / Interleave (programmable)

- Auto Precharge / All Bank Precharge controlled by A10

- Support concurrent Auto Precharge

- 4096 refresh cycles / 64ms (4 banks concurrent refresh)

- Auto Refresh and Self Refresh

- Row address A0-11 / Column address A0-8

- SSTL_2 Interface

- Package 400-mil, 66-pin Thin Small Outline Package (TSOP II) with 0.65mm lead pitch

A3S64D40GTP A3S56D40GTP ZENTEL DDR1 SDRAM