A3S64D40GTP A3S56D40GTP A3S28D40JTP ZENTEL DDR1 SDRAM -Shenzhen JYWY Electronics Co., Ltd.

Product

ZILLTEK

ZILLTEK Technology was established in 2005 in Taiwan.ZILLTEK is a professional analog and mixed signal IC design company. Since its establishment, it has been actively betting on R&D resources and rapidly developing new products.
ZILLTEK product line includes touch screen control ICs, power management ICs (A/DC/DC conversion, B. AC/DC conversion), white LED drivers and MEMS Microphone sensors, etc., which are mainly used for consumer products. Such as wireless broadband, data communication (AP routers, IAD, GPON, etc.) USB 3.0 applications (Pen-Driver, SSD, hard disk, etc.), LCD TVs, monitors, set-top boxes, surveillance (CCTV, IP-CAM, baby monitors, etc.) , tablet, MID, PDA, DVD player, IA, Smart phone, NoteBook products, etc.

A3S64D40GTP A3S56D40GTP A3S28D40JTP ZENTEL DDR1 SDRAM

A3S28D40JTP is a 4-bank x 2,097,152-word
x 16bit double data rate synchronous DRAM ,
with SSTL_2 interface. All control and address signals
are referenced to the rising edge of CLK.
Input data is registered on both edges of data strobe ,
and output data and data strobe are referenced on both edges of CLK.
The A3S28D40JTP achieves very high speed clock rate up to 200 MHz .

A3S64D40GTP A3S56D40GTP ZENTEL DDR1 SDRAM

FEATURES

-VDD=VDDQ=2.5V+0.2V

- Operating Temperature:

Commercial: 0 ~ 70℃

Industrial : -40 ~ 85℃

- Double data rate architecture ; two data transfers per clock cycle.

- Bidirectional , data strobe (DQS) is transmitted/received with data

- Differential clock input (CLK and /CLK)

- DLL aligns DQ and DQS transitions with CLK transitions edges of DQS

- Commands entered on each positive CLK edge ;

- Data and data mask referenced to both edges of DQS

- 4 bank operation controlled by BA0 , BA1 (Bank Address)

- CAS latency 2 / 2.5 / 3 (programmable) ;

- Burst length 2 / 4 / 8 (programmable)

- Burst type: Sequential / Interleave (programmable)

- Auto Precharge / All Bank Precharge controlled by A10

- Support concurrent Auto Precharge

- 4096 refresh cycles / 64ms (4 banks concurrent refresh)

- Auto Refresh and Self Refresh

- Row address A0-11 / Column address A0-8

- SSTL_2 Interface

- Package 400-mil, 66-pin Thin Small Outline Package (TSOP II) with 0.65mm lead pitch

A3S64D40GTP A3S56D40GTP ZENTEL DDR1 SDRAM